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product structure silicon monolithic integrated circuit this product has no designed protection against radioactive ra ys 1/26 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 2014 rohm co., ltd. all rights reserved. tsz22111 ? 14 ? 001 www.rohm.com serial eeprom series standard eeprom wlcsp eeprom brc h064gwz-3 general description br ch064gwz- 3 is a 64kbit serial eeprom of i 2 c bus interface method features ? completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock (scl) and serial data (sda) ? other devices than eeprom can be connected to the same port, saving microcontroller port ? 1.6v to 5.5v single power source operation most suitable for battery u se ? 1.6v to 5.5v wide limit of operating voltage , possible fast mode 400khz operation ? up to 32 byte in page write mode ? bit format 8k x 8 ? self-timed programming cycle ? low current consumption ? prevention o f write mistake ? write (write protect) function a dded ? prevention of write mistake at low voltage ? more than 1 million write cycles ? more than 40 years data retention ? noise filter built in scl / sda terminal ? initial delivery state ffh packages w( typ) x d(typ) x h(max) ucsp30 l1 a 1.50mm x1.00mm x 0. 33 mm datashee t downloaded from: http:///
datasheet 2/ 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com absolute maximum ratings (ta= 25 c ) parameter symbol rating unit remark supply voltage v cc -0.3 to +6.5 v power dissipation pd 0.22(ucsp30 l1 a) w derate by 2.2mw/c when operating above ta=25c storage temperature tstg -65 to +1 25 c operating temperature topr - 40 to + 85 c input voltage/ output voltage - -0.3 t o vcc+1.0 v the max value of input voltage/output voltage is not over 6.5v . when the pulse width is 50ns or less, the min value of input voltage/output voltage is not below 1.0v . junction temperature tjmax 150 c junction temperature at the storage condition caution : operating the ic over the absolute maximum ratings may dam age the ic. the damage can either be a short circuit between p ins or an open circuit between pins and the internal circuitry. therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the ic is operated over the absolute maximum ratings. memory cell characteristics (ta=25c, vcc=1.6v to 5.5v) parameter limit unit min typ max write cycles (note 1) 1,000,000 - - times data retention (note 1) 40 - - years (note 1) not 100% tested recommended operating ratings parameter symbol rating unit power source voltage vcc 1.6 to 5.5 v input voltage v in 0 to vcc dc characteristics ( unless otherwise specified, ta =- 40 c to +85 c , vcc=1.6v to 5.5v ) parameter symbol limit unit conditions min typ max input high voltage1 v ih1 0.7vcc - vcc+1.0 v 1.7v vcc 5.5v input low voltage1 v il1 -0.3 (note2) - +0.3vcc v 1.7v vcc 5.5v in put high voltage2 v ih 2 0. 8vcc - vcc+1.0 v 1.6v vcc 1.7v input low voltage2 v il 2 -0.3 (note2) - +0.2vcc v 1.6v vcc 1.7v output low voltage1 v ol1 - - 0.4 v i ol =3.0 ma , 2.5v vcc 5.5v (sda) output low voltage2 v ol2 - - 0.2 v i ol =0.7 ma , 1.6v vcc 2.5v (sda) input leakage current i li -1 - +1 a v in =0 to vcc output leakage current i lo -1 - +1 a v out =0 to vcc (sda) supply current (write) i cc1 - - 2.0 ma vcc=5.5v, f scl =400khz, t wr =5ms, byte write, page write supply current (read) i cc2 - - 0.5 ma vcc=5 .5 v, f scl =400k hz random read, current read , sequential read wp=gnd or vcc standby current i sb - - 2.0 a vcc=5.5v, sda ? scl=vcc wp=gnd or vcc, test=gnd or vcc (note2) when the pulse width is 50ns or less, it is -1.0v. downloaded from: http:///
datasheet 3/ 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com ac characteristics (unless otherwise specified, ta=- 40 c to +85c, vcc= 1.6v to 5.5v) parameter symbol limit unit min typ max clock frequency f scl - - 400 khz data clock high period t high 0.6 - - s data clock low period t low 1.2 - - s sda,scl(input) rise time (note 1) t r - - 1.0 s sda,scl (input)fall time (note 1) t f1 - - 1.0 s sda(output)fall time (note 1) t f2 - - 0.3 s start condition hold time t hd:sta 0.6 - - s start condition setup time t su:sta 0.6 - - s input data hold time t hd:dat 0 - - ns input data setup time t su:dat 100 - - ns output data delay time t pd 0.1 - 0.9 s output data hold time t dh 0.1 - - s stop condition setup time t su:sto 0.6 - - s bus free time t buf 1.2 - - s write cycle time t wr - - 5 ms noise spike width (sda and scl) t i - - 0.1 s wp hold time t hd:wp 1.0 - - s wp setup time t su:wp 0.1 - - s wp high period t high:wp 1.0 - - s (note 1) not 100% tested. condition input data level: v il =0.2vcc v ih =0.8vcc input data timing reference level: 0.3vcc/0.7vcc output data timing reference level: 0.3vcc/0.7vcc rise/fall time : 20ns serial input / outpu t timing input read at the rise edge of scl data output in sync with the fall of scl figure 1.-(a). serial input / output timing figure 1.-(b) start-stop bit timing figure 1.-(c). write cycle timing figure 1.-(d). wp timing at write execution figure 1.-(e). wp timing at write cancel 70 % 70 % tsu:sta thd:sta start condition tsu:sto stop condition 30 % 30 % 70 % 70 % d0 ack twr write data (n -th address) start condition stop condition 70 % 70 % data(1) d0 ack d1 data(n) ack twr 30 % 70 % stop condition thd:wp tsu:wp 30 % ata(1) ata(n) ack gh:wp 70 % 70 % twr 70 % 70 % data(1) d0 d1 ack data(n) ack thigh:wp 70 % 70 % twr 70 % scl sda( ) sda( ) tr tf1 thigh tsu:dat tlow thd:dat tdh tpd tbuf thd:sta 70% 30% 70% 70% 30% 70% 70% 30% 30% 70% 70% 30% 70% 70% 70% 70% 30% 30% 30% 30% tf2 (input) (output) downloaded from: http:///
datasheet 4/ 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com block diagram figure 2. block diagram pin configuration figure 3. pin configuration (bottom view) pin descriptions land no. terminal name input / output descriptions b3 test input slave address setting b2 gnd - reference voltage of all input / output, 0v b1 sda input / output slave and word address serial data input, serial data output a3 v cc - power supply a2 wp input write protect terminal a1 scl input serial clock input b1 b2 a1 a2 1 2 b a a b sda gnd gnd sda scl wp test vcc vcc b3 a3 3 gnd 64 kbit eeprom array address decoder slave, word address register data register control logic high voltage gen. v cc level detect 13bit 13bit 8bit ack start stop test wp vcc scl sda downloaded from: http:///
datasheet 5/ 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 6. output low voltage1 vs output low current (vcc=2. 5v ) figure 7 . output low voltage2 vs output low current (vcc=1.6 v) figure 4. input high voltage1,2, vs supply voltage figure 5. input low voltage1,2 vs supply voltage typical performance curves 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 output low current: i ol (ma) output low voltage1: v ol1 (v) spec ta=-40c ta= 25c ta= 85c 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 output low current: i ol (ma) output low voltage2: v ol2 (v) spec ta=-40c ta= 25c ta= 85c 0 1 2 3 4 5 6 0 1 2 3 4 5 6 supply voltage: vcc(v) input low voltage1,2: v il1,2 (v) spec ta=-40c ta= 25c ta= 85c 0 1 2 3 4 5 6 0 1 2 3 4 5 6 supply voltage: vcc(v) input high voltage : v ih1,2 (v) ta=-40c ta= 25c ta= 85c spec downloaded from: http:///
datasheet 6/ 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 11. supply current (read ) vs supply voltage (f scl =400khz) figure 8. input leakage current vs supply voltage (scl, wp, test) figure 9. output leakage current vs supply voltage (sda) figure 10. supply current (write) vs supply voltage (f scl =400khz) typical performance curves \ continued 0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 6 supply voltage: vcc(v) supply current (write): i cc1 (ma) spec ta=-40c ta= 25c ta= 85c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) supply current (read): i cc2 (ma) spec ta=-40c ta= 25c ta= 85c 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 supply voltage: vcc(v) input leakage current: i li (a) spec ta=-40c ta= 25c ta= 85c 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 supply voltage: vcc(v) output leakage current: i lo (a) ta=-40 ta= 25 ta= 85 spec downloaded from: http:///
datasheet 7/ 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 13. clock frequency vs supply voltage figure 14. data clock high period vs supply voltage figure 12. standby current vs supply voltage figure 15. data clock low period vs supply voltage typical performance curves \ continued 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6 supply voltage: vcc(v) standby current: i sb (a) spec ta=-40c ta= 25c ta= 85c 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 supply voltage: vcc(v) data clock high period : t high (s) spec ta=-40c ta= 25c ta= 85c 0 0.3 0.6 0.9 1.2 1.5 0 1 2 3 4 5 6 supply voltage: vcc(v) data clock low period : t low (s) spec ta=-40c ta= 25c ta= 85c 0.1 1 10 100 1000 10000 0 1 2 3 4 5 6 supply voltage: vcc(v) clock frequency: f scl (khz) spec ta=-40c ta= 25c ta= 85c downloaded from: http:///
datasheet 8/ 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 17. start condition setup time vs supply voltage figure 18. input data hold time vs supply voltage (high) figure 16. start condition hold time vs supply voltage figure 19. input data hold time vs supply voltage (low) typical performance curves \ continued 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 supply voltage: vcc(v) start condition hold time: t hd:sta (s) spec ta=-40c ta= 25c ta= 85c -0.2 0 0.2 0.4 0.6 0.8 1 0 1 2 3 4 5 6 supply voltage: vcc(v) start condition setup time: t su:sta (s) spec ta=-40c ta= 25c ta= 85c -200 -150 -100 -50 0 50 0 1 2 3 4 5 6 supply voltage: vcc(v) input data hold time: t hd:dat (ns) spec ta=-40c ta= 25c ta= 85c -200 -150 -100 -50 0 50 0 1 2 3 4 5 6 supply voltage: vcc(v) input data hold time: t hd:dat (ns) spec ta=-40c ta= 25c ta= 85c downloaded from: http:///
datasheet 9/ 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 23. output data delay time vs supply voltage (high) figure 21. input data setup time vs supply voltage (low) figure 22. output data delay time vs supply voltage (low) figure 20. input data setup time vs supply voltage (high) typical performance curves \ continued -200 -100 0 100 200 300 0 1 2 3 4 5 6 supply voltage: vcc(v) input data setup time: t su:dat (ns) spec ta=-40c ta= 25c ta= 85c -200 -100 0 100 200 300 0 1 2 3 4 5 6 supply voltage: vcc(v) input data setup time: t su:dat (ns) spec ta=-40c ta= 25c ta= 85c 0 0.5 1 1.5 2 0 1 2 3 4 5 6 supply voltage: vcc(v) output data delay time: t pd (s) spec spec ta=-40c ta= 25c ta= 85c 0 0.5 1 1.5 2 0 1 2 3 4 5 6 supply voltage: vcc(v) output data delay time: t pd (s) spec spec ta=-40c ta= 25c ta= 85c downloaded from: http:///
datasheet 10 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 24. stop condition setup time vs supply voltage figure 27. noise spike width vs supply voltage (scl high) figure 25. bus free time vs supply voltage figure 26. write cycle time vs supply voltage typical performance curves \ continued -0.5 0 0.5 1 1.5 2 0 1 2 3 4 5 6 supply voltage: vcc(v) stop condition setup time: t su:sto (s) spec ta=-40c ta= 25c ta= 85c 0 0.5 1 1.5 2 0 1 2 3 4 5 6 supply voltage: vcc(v) bus free time: t buf (s) spec ta=-40c ta= 25c ta= 85c 0 1 2 3 4 5 6 0 1 2 3 4 5 6 supply voltage: vcc(v) write cycle time: t wr (ms) spec ta=-40c ta= 25c ta= 85c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) noise spike width (scl high):ti(s) spec ta=-40c ta= 25c ta= 85c downloaded from: http:///
datasheet 11 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 29. noise spike width vs supply voltage (sda high) figure 30. sda noise spike width (low) vs supply voltage (sda low) figure 31. wp hold time vs supply voltage figure 28. noise spike width vs supply voltage (scl l ow ) typical performance curves \ continued 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) noise spike width (scl low): ti(s) spec ta=-40c ta= 25c ta= 85c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) noise spike width (sda low): ti(s) spec ta=-40c ta= 25c ta= 85c 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 supply voltage: vcc(v) wp hold time: t hd:wp (s) spec ta=-40c ta= 25c ta= 85c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 1 2 3 4 5 6 supply voltage: vcc(v) noise spike width (sda high): ti(s) spec ta=-40c ta= 25c ta= 85c downloaded from: http:///
datasheet 12 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com figure 32. wp setup time vs supply voltage figure 33. wp high period vs supply voltage typical performance curves \ continued -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0 1 2 3 4 5 6 supply voltage: vcc(v) wp setup time: t su:wp (s) spec ta=-40c ta= 25c ta= 85c 0 0.2 0.4 0.6 0.8 1 1.2 0 1 2 3 4 5 6 supply voltage: vcc(v) wp high period: t high:wp ( s) spec ta=-40c ta= 25c ta= 85c downloaded from: http:///
datasheet 13 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com timing chart 1. i 2 c bus data communication i 2 c bus data communication starts by start condition input, and e nds by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus data communication with several devices is possible by connect ing with 2 communication lines: serial data (sda) and serial clock (scl). among the devices, there should be a master that generates clock and control communication start and end. the rest become slave wh ich are controlled by an address peculiar to each device , like this eeprom. the device that outputs data to the bus during data communication is called transmitter , and the device that receives data is called receiver . 2. start condition (start bit recognition ) (1) before executing each command, start condition (start bi t) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. (2) this ic always detects whether sda and scl are in start condition (sta rt bit) or not, therefore, unless this condition is satisfied, any command cannot be executed. 3. stop condition (stop bit recognition) (1) each command can be ended by a stop condition (stop bit) where sda goes from 'low' to 'high' while scl is 'high'. 4. acknowledge (ack) signal (1) th e acknowledge (ack) signal is a software rule to show whether dat a transfer has been made normally or not. in a master-slave communication, the device (ex. -com sends sl ave address input for write or read command, to this ic ) at the transmitter (sending) side releases the bus after ou tput of 8bit data. (2) the device (ex. this ic receives the slave address inpu t for write or read command from the -com) at the receiver (receiving) side sets sda 'low' during the 9 th clock cycle, and outputs acknowledge signal (ack signal ) showing that it has received the 8bit data. (3) this ic, after recognizing start condition and slave address (8 bit), outputs acknowledge signal (ack signal) 'low'. (4) after receiving 8bit data (word address and write data) du ring each write operation, this ic outputs acknowledge signal (ack signal) 'low'.. (5) during read operation, this ic outputs 8bit data (read data) and detects acknowledge signal (ack signal) 'low' . when acknowledge signal (ack signal) is detected, and stop c ondition is not sent from the master (-com) side, this ic continues to output data. when acknowledge signal ( ack signal) is not detected, this ic stops data transfer, recognizes stop condition (stop bit), and ends read operation . then this ic becomes ready for another transmission. 5. device addressing (1) slave address comes after start condition from master. (2) the significant 4 bits of slave address are used for recogni zing a device type. the device code of this ic is fixed to ' 1010 '. (3) next slave addresses (a2 0 0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. (4) the most insignificant bit ( w/r --- read / write ) of slave address is used for designating write or read operation, and is as shown below. setting w/r to 0 ------- write (setting 0 to word address setting of random read ) setting w/r to 1 ------- read slave address maximum number of connected buses 1 0 1 0 a2 0 0 r/ w DD 2 8 9 8 9 8 9 s p condition condition ack stop ack data data address start r/w ack 1-7 sda scl 1-7 1-7 figure 34. data transfer timing downloaded from: http:///
datasheet 14 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com write command 1. write cycle (1) arbitrary data can be written to this eeprom. when writ ing only 1 byte, byte write is normally used, and wh en writ ing continuous data of 2 bytes or more, simultaneous write is possible by p age write cycle. up to 32 arbitrary bytes can be written. (2) during internal write execution, all input commands are igno red, therefore ack is not returned. (3) data is written to the address designated by word address (n-th address) (4) by issuing stop bit after 8bit data input, internal write to me mory cell starts. (5) when internal write is started, command is not accepted for t wr (5ms at maximum). (6) using page write cycle, writ ing in bulk is done as follows : when data of more than 32 bytes is sent, the bytes in excess overwrites the data already sent first. (refer to "internal address increment".) (7) as for page write cycle where 2 or more bytes of data is inten ded to be written, after the 8 significant bi ts of word address are designated arbitrarily, only the value of 5 least sig nificant bits in the address is incremented internally, so that data up to 32 addresses of memory onl y can be written. 1 page=32bytes, but the page write cycle time is 5ms at maximu m for 32byte bulk write. it does not stand 5ms at maximum 32byte=160ms(max) 2. internal address increment page write mode 3. write protect (wp) terminal write protect (wp) function when wp terminal is set at vcc (h level), data rewrite of al l addresses is prohibited. when it is set at gnd (l level), d ata rewrite of all address is enabled. be sure to connect this t erminal to vcc or gnd, or control it to h level or l level. do not leave it open. at extremely low voltage at power on / off, by setting the wp terminal 'h', write error can be prevented. *don't care bit figure 35. byte write cycle figure 36. page write cycle d0 d7 a c k 2nd word address(n) wa 0 * wa 12 wa 11 for example, when it is started from address 1eh, then, increment is made as below, 1eh 1fh 00h 01h ??? please take note. 1eh ??? 1e in hexadecimal, therefore, 00011110 becomes a binary number. wa7 wa6 wa5 wa4 wa3 wa2 wa1 wa0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 increment 1eh significant bit is fixed. no digit up *don't care bit w r i t e s t a r t r / w a c k s t o p 1st word address(n) sda line a c k a c k data(n+31) a c k slave address 1 0 0 1 d0 data(n) * * a2 0 0 0 a2 1 1 0 0 w r i t e s t a r t r / w s t o p 1st word ad dress data slave address 0 d0 a c k sda line a c k a c k * wa 12 wa 11 wa 0 a c k 2nd word address d7 * * downloaded from: http:///
datasheet 15 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com read command 1. read cycle read cycle is when data of eeprom is read. read cycle could be random read cycle or current read cycle. random read cycle is a command to read data by designating a specific address, and is used generally. current read cyc le is a command to read data of internal address register without des ignating an address, and is used when to verify just after write cycle. in both the read cycles, sequential read cycle is available where the next address data can be read i n succession. (1) in random read cycle, data of designated word address can be rea d. (2) when the command just before current read cycle is ran dom read cycle, current read cycle (each including sequen tial read cycle), data of incremented last read address (n)- th , i.e., data of the (n+1)-th address, is output. (3) when ack signal 'low' after d0 is detected, and stop cond ition is not sent from master (-com) side, the next address data can be read in succession. (4) read cycle is ended by stop condition where 'h' is in put to ack signal after d0 and sda signal goes from l to h while scl signal is 'h ' . (5) when 'h' is not input to ack signal after d0, sequential read gets in, and the next data is output. therefore, read command cycle cannot be ended. to end the read command cycle, be sure to input 'h' to ack signal after d0, and the stop condition where sda goes from l to h while scl signal is 'h'. (6) sequential read is ended by stop condition where 'h' is input to ack signal after arbitrary d0 and sda is asserted from l to h while scl signal is 'h'. figure 37. random read cycle *don't care bit figure 38. current read cycle figure 39. sequential read cycle (in the case of current read cycle) w r i t e s t a r t r / w a c k s t o p 1st word address sda line a c k a c k data(n) a c k slave address 1 0 0 1 d7 d0 2nd word address (n) a c k s t a r t slave address 1 0 0 0 1 0 r / w r e a d wa 0 * wa 12 wa 11 * * a2 0 0 a2 0 0 s t a r t s t o p sda line a c k data(n) a c k slave address 1 0 0 0 1 0 0 a2 d0 d7 r / w r e a d r e a d s t a r t r / w a c k s t o p data(n) sda line a c k a c k data(n+x) a c k slave address 1 0 0 0 1 0 0 0 a2 d0 d7 d0 d7 downloaded from: http:///
datasheet 16 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com software r eset software reset is executed to avoid malfunction after power on and during command input. software reset has several kinds and 3 kinds of them are shown in the figure below . (refer to figure 40.-(a), figure 40.-(b) , and figure 40.-(c).) within the dummy clock input area, the sda bus is released ('h' by pull up) and ack output and read data '0' (both 'l' lev el) may be output from eeprom. therefore, if 'h' is input forcibly, outp ut may conflict and over current may flow, leading to instantaneous power failure of system power source or influence u pon devices. acknowledge polling during internal write execution, all input commands are ignore d, therefore ack is not returned. during internal automatic write execution after write cycle input, next command (slav e address) is sent.if the first ack signal sends back 'l' , then it means end of write operation , else 'h' is returned , which means writing is still in progress. by the use of ac knowledge polling, next command can be executed without waiting for t wr = 5ms. to write continuously, w/r = 0, then to carry out current read cycle after write, slave ad dress with w/r = 1 is sent. i f ack signal sends back 'l', then execute word address input and da ta output and so forth. 1 2 13 14 scl dummy clock14 start2 scl figure 40.-(a) the case of dummy clock 14 + start+start+ command input start command from start input. 2 1 8 9 dummy clock 9 start figure 40.-(b) the case of start + dummy clock9 + start + command input start normal comm and normal command normal command normal command start 9 sda sda scl sd a 1 2 3 8 9 7 figure 40.-(c) start9 + command input normal command normal command sda slave address word address s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is returned. after completion of internal write, ack=low is returned, so input next word address and data in succession. t wr t wr second write command s t a r t s t a r t s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l figure 41. case of continuous write by acknowledge polling downloaded from: http:///
datasheet 17 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to cancel write cycle and so on , pay attention to the following wp valid timing. during write cycle execution, inside cancel valid are a, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in d0 of data(in page write cycle, the first byte data) is the cancel inv alid area. wp input in this area becomes don't care . the area from the rise of scl to take in d0 to the stop cond ition input is the cancel valid area. furthermore, after the execution of forced end b y wp, the ic enters standby status . command cancel by start condition and s top condition during command input, by continuously inputting start condi tion and stop condition, command can be cancelled. (figu re 43.) however, within ack output area and during data read, sda bu s may output 'l'. in this case, start condition and stop condition cannot be input, so reset is not available. t herefore, execute software reset. when command is cancelle d by start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined. therefore, it is not possible to carry out current read cycle in succession. to carry out read cycle in succession, carry out random read cycle. ? rise of d0 taken clock scl d0 ack enlarged view scl sda ack d0 ? rise of sda sda wp wp cancel invalid area wp cancel valid area data is not written. figure 42. wp valid timing slave address d7 d6 d5 d4 d3 d2 d1 d0 data t wr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address figure 43. case of cancel by start, stop condition during slave ad dress input scl sda 1 1 0 0 start condition stop condition enlarged view wp cancel invalid area downloaded from: http:///
datasheet 18 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com i/o peripheral circuit 1. pull up resistance of sda terminal sda is nmos open drain, so it requires a pull up resist or . as for this resistance value (r pu ), select an appropriate value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, operating frequency is limited. the smaller the r pu , the larger is the supply current (read). 2. maximum value of r pu the maximum value of r pu is determined by the following factors: (1)sda rise time to be determined by the capacitance (c bus ) of bus line and r pu of sda should be t r or low er . furthermore, ac timing should be satisfied even when sda rise time is slow. (2)the bus electric potential a to be determined by the input current leak total (i l ) of the device connected to the bus with output of 'h' to the sda line and r pu should sufficiently secure the input 'h' level (v ih ) of microcontroller and eeprom including recommended noise margin of 0.2vcc. ih cc pu l cc v v 0.2 - ri- v ? l ih cc pu i v v r - 8.0 ? ex.) v cc =3v i l =10a v ih =0.7 v cc from(2) 6- 10 10 3 7.0-3 8.0 ? ? ? ? pu r ] [ 30 ? ? ? k 3. minimum value of r pu the minimum value of r pu is determined by the following factors: (1)when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. ol pu ol cc i r v v ? - ol ol cc pu i v v r - ? (2)v olmax =0.4v should secure the input 'l' level (v il ) of microcontroller and eeprom including the recommended noise margin of 0.1vcc. cc il olmax 0.1v - v v ? ex.) v cc =3v, v ol =0.4v, i ol =3ma, microcontroller, eeprom v il =0.3vcc from (1) -3 10 3 4.0-3 ? ? pu r ] [ 867 ? ? and ][ . = v 4 0 v ol 3 3 0 v il . = ][ . = v 9 0 therefore, the condition (2) is satisfied. 4. pull-up resistance of scl terminal when scl control is made at the cmos output port, there is no need for a pull up resistor. but when there is a time where scl becomes 'hi-z', add a pull up resist or . as for the pull up resistor value, one of several k ? to several ten k ? is recommended in consideration of drive performance of output port o f microcontroller. figure 44. i/o circuit diagram microcontroller r pu a sda terminal i l i l bus line capacity c bus eeprom downloaded from: http:///
datasheet 19 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com cautions on microcontroller connection 1. r s in i 2 c bus, it is recommended that sda port is of open drain input/outp ut. however, when us ing cmos input / output of tri state to sda port, insert a series resistance r s between the pull up resist or r pu and the sda terminal of eeprom. this is to control over current that may occur when pmos of th e microcontroller and nmos of eeprom are turned on simultaneously. r s also plays the role of protecti ng the sda terminal against surge. therefore, even when sda port is open drain input/output, r s can be used. 2. maximum value of r s the maximum value of r s is determined by the following relations: (1 )sda rise time to be determined by the capacitance (c bus ) of bus line and r pu of sda should be t r or low er . furthermore, ac timing should be satisfied even when sda rise time is s low. (2)the bus electric potential a to be determined by r pu and r s the moment when eeprom outputs 'l' to sda bus should sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin of 0 .1vcc. il cc ol s pu s ol cc v v v r r r v v ? ? ? ? ? 1.0 ) - ( pu il cc cc ol il s r v v v v v r ? ? - 1.1 1.0- - ex) v cc =3v v il =0.3v cc v ol =0.4v r pu =20k ? 3 10 20 3 0.3 -3 1.1 3 0.1 -4.0-3 3.0 ? ? ? ? ? ? ? s r ] [ 67 .1 ? ? k 3. minimum value of r s the minimum value of r s is determined by over current at bus collision. when over cu rrent flows, noises in power source line and instantaneous power failure of power source may oc cur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowab le current in consideration of the impedance of power so urce line in set and so forth. set the over current to eeprom at 10ma or low er . i r v s cc ? i v rs cc ? ? ex) v cc =3v i=10ma -3 10 10 3 ? ? rs ] [ 300 ? ? r pu microcontroller r s eeprom fi gure 45. i/o circuit diagram figure 46. input / output collision timing ack 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda microcontroller eeprom 'l'output r s r pu 'h' output over current i figure 48. i/o circuit diagram figure 47. i/o circuit diagram r pu micro controller r s eeprom i ol a bus line capacity c bus v ol v cc v il downloaded from: http:///
datasheet 20 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com i/o equivalen ce circuit 1. input (scl, wp , test) 2 . input / output (sda) figure 49. input pin circuit diagram figure 50. input / output pin circuit diagram downloaded from: http:///
datasheet 21 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com power-up/down conditions at power on, the ic s internal circuits may go through unstable low voltage area as the vcc rises , making the ic s interna l logic circuit not completely reset, hence, malfunction ma y occur. to prevent this, the ic is equipped with por circui t and lvcc circuit. to assure the operation, observe the following con ditions at power on. 1. set sda = 'h' and scl ='l' or 'h 2. start power source so as to satisfy the recommended condition s of t r , t off , and v bot for operating por circuit. t off t r v bot 0 v cc 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be observed, take t he following countermeasures. (1 ) in the case when the above condition 1 cannot be observed s uch that sda becomes 'l' at power on. control scl and sda as shown below, to make scl and sda, 'h' and 'h'. (2 ) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(page 16 ). (3 ) in the case when the above conditions 1 and 2 cannot be obse rved. carry out (1 ), and then carry out (2). low voltage malfunction prevention function lvcc circuit prevents data rewrite operation at low power an d prevents write error. at lvcc voltage (typ =1.2v) or below, data rewrite is prevented. noise countermeasures 1. bypass capacitor when noise or surge gets in the power source line, malfu nction may occur, therefore, it is recommended to connect a bypass capacitor (0.1f) between the ic s vcc and gnd pins . connect the capacitor as close to the ic as possible. in addition, it is also recommended to attach a bypass capaci tor between the board s vcc and gnd. recommended conditions of t r , t off ,v bo t t r t off v bot 10ms or below 10ms or larger 0.3v or below 100ms or below 10ms or larger 0.2v or below figure 51. rise waveform diagr am figure 52. when scl= 'h ' and sda= 'l' figure 53. when scl='l ' and sda='l' t low t su:dat t dh after vcc becomes stable scl v cc sda t su:dat after vcc becomes stable downloaded from: http:///
datasheet 22 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com operational notes 1. reverse connection of power supply connecting the power supply in reverse polarity can damage the ic. take precautions against reverse polarity when connecting the power supply, such as mounting an extern al diode between the power supply and the ic s power supply pin s. 2. power supply lines design the pcb layout pattern to provide low impedance supply lines. separate the ground and supply lines of the digital and analog blocks to prevent noise in the grou nd and supply lines of the digital block from affecting th e analog block. furthermore, connect a capacitor to ground at all power su pply pins . consider the effect of temperature and aging on the capacitance value when using electrolytic capa citors. 3. ground voltage ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. ground wiring pattern when using both small-signal and large-current ground trac es, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small- signal ground caused by large currents. also ensure that the ground traces of external components do not cause variations on the ground voltage. the ground lines must be as short and thick as possible to reduce line impedance. 5. thermal consideration should by any chance the power dissipation rating be exc eeded the rise in temperature of the chip may result in deterioration of the properties of the chip. the absolute m aximum rating of the pd stated in this specification is w hen the ic is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. in case of exceeding this absolute maximum rating, increase the board size and copper area to prevent excee ding the pd rating. 6. recommended operating conditions these conditions represent a range within which the expe cted characteristics of the ic can be approximately obtained . the electrical characteristics are guaranteed under the condi tions of each parameter. 7. inrush current when power is first supplied to the ic, it is possible that the int ernal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and del ays, especially if the ic has more than one power supply. therefore, give special consideration to power coupli ng capacitance, power wiring, width of ground wiring, and routing of connections. 8. operation under strong electromagnetic field operating the ic in the presence of a strong electromagnetic field ma y cause the ic to malfunction. 9. testing on application boards when testing the ic on an application board, connecting a capacitor directly to a low-impedance output pin may subject the ic to stress. always discharge capacitors comple tely after each process or step. the ics po wer supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. to prevent damage from static discharge, ground t he ic during assembly and use similar precautions during transport and storage. 10. inter-pin short and mounting errors ensure that the direction and position are correct when mountin g the ic on the pcb. incorrect mounting may result in damaging the ic. avoid nearby pins being shorted to each other especially to ground, power supply and output pin . inter-pin shorts could be due to many reasons such as metal parti cles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during as sembly to name a few. downloaded from: http:///
datasheet 23 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com operational notes C continued 11. unused input pins input pin s of an ic are often connected to the gate of a mos transistor. the gate has extremely high impedance and extremely low capacitance. if left unconnected, the elec tric field from the outside can easily charge it. the smal l charge acquired in this way is enough to produce a signi ficant effect on the conduction through the transistor and cause unexpected operation of the ic. so unless otherwise spe cified, unused input pin s should be connected to the power supply or ground line. 12. rega rd ing the input pin of the ic in the construction of this ic, p-n junctions are inevitabl y formed creating parasitic diodes or transistors. the operation of these parasitic elements can result in mutu al interference among circuits, operational faults, or physi cal damage. therefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin lower than the ground voltage should be avoid ed. furthermore, do not apply a voltage to the input pins wh en no power supply voltage is applied to the ic. even if the power suppl y voltage is applied, make sure that the input pin s have voltages within the values specified in the electrical chara cteristics of this ic. downloaded from: http:///
datasheet 24 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com part numbering b r c h 0 6 4 g w z - 3 e 2 bus type c i 2 c revision capacity 064=64k package gwz ucsp30 l1 a process code packaging and forming specification e2 : embossed tape and reel downloaded from: http:///
datasheet 25 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com physical dimension tape and reel information package name ucsp30 l1 a(brch064gwz- 3) 3 < tape and reel information > tape embossed carrier tape quantity 6000pcs direction of feed e2 the direction is the pin 1 of product is at the upper left whe n you hold reel on the left hand and you pull out the tape on the rig ht hand reel direction of feed 1pin 1234 1234 1234 1234 1234 1234 3 0.4 a 1.5 0. 05 b 1 0. 06 s 1pin mark 0.33max p=0.4 2 s 2 b 0. 35 0. 05 0.06 a 0.3 0.05 a 0. 05 1.0 0.05 6- 0. 20 0. 05 lot no. b adm (unit : mm) downloaded from: http:///
datasheet 26 / 26 brch064gwz-3 tsz02201-0r2r0g100 72 0-1-2 11.may.2015 rev. 00 2 ? 201 4 rohm co., ltd. all rights reserved. tsz22111 ? 15 ? 001 www.rohm.com marking diagram revision history date revision changes 16 .jan.2015 00 1 new release 11 .may.2015 002 correction of marking diagram from adjm to adm ucsp30 l1 a(brch064gwz- 3) (top view) ad m part number marking lot number 1pin mark downloaded from: http:///
datasheet d a t a s h e e t notice-pga-e rev.001 ? 2015 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufac tured for application in ordinary elec tronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electroni c appliances, amusement equipment, etc.). if you intend to use our products in devices requiring ex tremely high reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecra ft, nuclear power controllers, fuel c ontrollers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property (specific applications), please consult with the rohm sale s representative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ro hms products for specific applications. (note1) medical equipment classification of the specific applications japan usa eu china class class class b class class ? class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe desi gn against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditio ns, as exemplified below. accordin gly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of an y rohms products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] use of our products in any types of liquid, incl uding water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products ar e exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed to static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing components, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (ev en if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subjec t to radiation-proof design. 5. please verify and confirm characteristics of the final or mounted products in using the products. 6. in particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse. is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading c ondition may negatively affect product performance and reliability. 7. de-rate power dissipation (pd) depending on ambient temper ature (ta). when used in seal ed area, confirm the actual ambient temperature. 8. confirm that operation temperat ure is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for fa ilure induced under deviant condi tion from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlori ne, bromine, etc.) flux is used, the resi due of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. if the flow sol dering method is preferred on a surface-mount products, please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:///
datasheet d a t a s h e e t notice-pga-e rev.001 ? 2015 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, pl ease allow a sufficient margin considering variations of the characteristics of the products and external components, including transient characteri stics, as well as static characteristics. 2. you agree that application notes, re ference designs, and associated data and in formation contained in this document are presented only as guidance for products use. theref ore, in case you use such information, you are solely responsible for it and you must exercise your own indepen dent verification and judgment in the use of such information contained in this document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take proper caution in your manufacturing process and storage so that voltage exceeding t he products maximum rating will not be applied to products. please take special care under dry condit ion (e.g. grounding of human body / equipment / solder iron, isolation from charged objects, se tting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriora te if the products are stor ed in the places where: [a] the products are exposed to sea winds or corros ive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to di rect sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm sol derability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the co rrect direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. use products within the specified time after opening a humidity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage time period. precaution for product label qr code printed on rohm products label is for rohms internal use only. precaution for disposition when disposing products please dispose them proper ly using an authorized industry waste company. precaution for foreign exchange and foreign trade act since concerned goods might be fallen under listed items of export control prescribed by foreign exchange and foreign trade act, please consult with rohm in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoi ng information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. rohm shall not have any obligations where the claims, actions or demands arising from the co mbination of the products with other articles such as components, circuits, systems or external equipment (including software). 3. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the products or the informati on contained in this document. pr ovided, however, that rohm will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the produc ts, subject to the terms and conditions herein. other precaution 1. this document may not be reprinted or reproduced, in whol e or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any wa y whatsoever the products and the related technical information contained in the products or this document for any military purposes, incl uding but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:///
datasheet datasheet notice C we rev.001 ? 201 5 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:///

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